To realize high speed and low power consumption in a bipolar transistor, it is necessary to reduce pattern size and lower junction capacitance. Conventionally it was attempted to reduce the pattern size and lower the junction capacitance by forming base lead-out electrodes by polycrystal silicon film (polysilicon film). For example, in the IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 5, October 1981, page 424 et seq., "A 3-ns 1-kbit RAM Using Super Self-Aligned Process Technology" Tetsushi TAKAI et al., the process of forming the base lead-out electrodes by boron doped polysilicon film is disclosed.
In the IEEE Journal, the integrated transistor structure using super self-aligned process technology is explained as follows.
"The spacing between n.sup.+ polysilicon emitter and p.sup.+ polysilicon base electrode is less than 1 .mu.m. These electrodes are separated during the self-aligned fabrication process using one photomask at the emitter pattern edge, together with the formation of the emitter area. PA0 A significant reduction in the external base region is achieved by this technology, which leads to lower base resistance and parasitic capacitances. PA0 The n.sup.+ polysilicon and p.sup.+ polysilicon are used for the diffusion source, as well as for the electrodes. These doped polysilicon electrodes make it possible to form a stable shallow junction, resulting in a high cutoff frequency. PA0 There are the p.sup.+ and p.sup.++ base regions around the emitter region. This p.sup.+ base region, formed by the self-aligned fabrication processes, stabilizes transistor performance, especially, the current gain h.sub.FE in the lower collector current region. PA0 The SiO.sub.2 film thickness on the p.sup.+ polysilicon, the n.sup.+ polysilicon and the p.sup.+ base region is about 0.25-0.3 .mu.m. The side wall of the emitter region is SiO.sub.2 and the emitter-base junction is flat, therefore, the emitter-base junction capacitance is smaller than that of conventional transistors." PA0 "The fabrication steps are same as the conventional bipolar IC process until a base diffused layer is formed. PA0 The subsequent steps are as follows. PA0 (1) After the base implantation process, undoped polysilicon is deposited. The unnecessary portions of polysilicon are oxidized. PA0 (2) Si.sub.3 N.sub.4 and SiO.sub.2 films are deposited. The SiO.sub.2 except for the emitter and collector contact is etched away. PA0 (3) Boron is implanted into the undoped polysilicon. The SiO.sub.2 fabricated in process stage (2) serves as a mask when boron is implanted. PA0 (4) Si.sub.3 N.sub.4 is etched with slight side-etching. The undoped polysilicon is etched away with submicrometer width by using the selective etch rate of the boron-implanted polysilicon, which is about 3 percent or less than that of the undoped polysilicon. PA0 (5) The silicon is oxidized. The Si.sub.3 N.sub.4 is etched away. Then the p.sup.+ base region is formed by boron implantation without a mask. Therefore, the p.sup.+ base region is formed by the self-aligned fabrication processes. PA0 (6) n-type impurity is doped into the undoped polysilicon, and then an emitter region is formed by diffusion. PA0 (7) Conventional processes are used for the rest of the fabrication steps."
Further, in the IEEE Journal, the fabrication steps are explained as follows.
However, the fabrication process disclosed in this IEEE Journal of Solid-State Circuits has the following problems.
(1) It is difficult to form the polysilicon film used as emitter electrode at high precision and finely.
That is, the polysilicon film used as emitter electrode is formed by etching the undoped polysilicon film which is faster in etching rate, using SiO.sub.2 film as mask, by making use of the difference in etching rate between the boron doped polysilicon film having boron ions doped, and undoped polysilicon film. However, when forming a boron doped polysilicon film, the area under the SiO.sub.2 film region also becomes a boron doped polysilicon film. Accordingly, in order that the undoped polysilicon film may be etched, it is necessary to side-etch an Si.sub.3 N.sub.4 film. Besides, in order to isolate the undoped polysilicon film and boron doped polysilicon film completely, it is required to etch for the portion of film thickness of undoped polysilicon film. As a result, at least a side etching corresponding to the portion of film thickness of undoped polysilicon film is left over. Therefore, the amount of side etching of undoped polysilicon film varies due to the effects of penetration of boron doped polysilicon film into the area under the SiO.sub.2 film region, side etching amount of Si.sub.3 N.sub.4 film, uneven film thickness of undoped polysilicon film, and fluctuations of etching time of undoped polysilicon film, etc. Accordingly, the pattern dimension of the undoped polysilicon film serving as emitter electrode varies, and it is hard to form finely at high precision.
(2) It is difficult to reduce the resistance of boron doped polysilicon film used as base lead-out electrode.
That is, the boron doped polysilicon film loses its Si by about half the thickness of SiO.sub.2 film due to its forming, and becomes thin and is consequently raised in the resistance.
Accordingly, if the film thickness is increased in order to lower the resistance of boron doped polysilicon film, as mentioned above, the side etch amount of the undoped polysilicon film in the area under SiO.sub.2 film region increases, and the precision of the pattern dimension of the undoped polysilicon film used as emitter electrode is lowered. At the same time, the spacing between the undoped polysilicon film and boron doped polysilicon film is widened, and the resistance of p.sup.+ diffusion layer increases and the junction capacitance also increases. In order to control the loss of boron doped polysilicon film due to oxidation, if the thickness of SiO.sub.2 film is reduced, the insulation of the SiO.sub.2 film may not be satisfied.
(3) Stress is likely to occur when forming SiO.sub.2 film.
That is, when SiO.sub.2 film is formed is after isolating the undoped polysilicon film and boron doped polysilicon film, the space between the undoped polysilicon film and boron doped polysilicon film is concave, and stress due to oxidation is concentrated in this concave area. In this case, the stress is larger when the spacing is narrower. Therefore, when the spacing is narrowed, defects due to stress are likely to occur, which may cause reduction of yield.
(4) It is difficult to form thinly the p.sup.+ diffusion layer serving as active base diffusion layer.
That is, since boron ions are directly implanted into the n-epitaxial layer, it is susceptible to channeling effect. Accordingly, implantation energy and implantation dope in ion implantation are limited, and impurity concentrations are high, and it is hard to form an active base diffusion layer shallow in the depth of diffusion.